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Cypress Semiconductor /psoc63 /SRSS /CLK_TRIM_PILO_CTL

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Interpret as CLK_TRIM_PILO_CTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PILO_CFREQ0PILO_OSC_TRIM 0PILO_COMP_TRIM 0PILO_NBIAS_TRIM 0PILO_RES_TRIM 0PILO_ISLOPE_TRIM 0PILO_VTDIFF_TRIM

Description

PILO Trim Register

Fields

PILO_CFREQ

Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz.
PILO_OSC_TRIM

Trim for current in oscillator block.
PILO_COMP_TRIM

Trim for comparator bias current.
PILO_NBIAS_TRIM

Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier
PILO_RES_TRIM

Trim for beta-multiplier branch current
PILO_ISLOPE_TRIM

Trim for beta-multiplier current slope
PILO_VTDIFF_TRIM

Trim for VT-DIFF output (internal power supply)

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data